The memory available to a microprocessor commonly includes special high speed memory referred to as cache memory or simply cache. Cache memory comprises an array of individual memory cells, each memory cell adapted to store one bit of data. A number of memory cells are arranged in a column connected by two conductors referred to as a bit line pair. The memory includes a number of such columns of memory cells. Data is written to or transferred from the memory cells via the bit line pair associated with each column of memory cells. A voltage signal in a "high" range on one bit line of the bit line pair represents one logical state while a voltage signal in a "high" range on the opposite bit line represents the opposite logical state. The memory cells are connected in rows by word lines which are used to activate a particular memory cell in a column and allow data, that is, one logical state or the other, to be written to or transferred from the particular cell.
A write driver is used to control the charge state of the bit line pairs during a writing operation to a memory cell within a column. The write driver comprises a circuit connected to the bit line pair which causes the bit lines in the pair to have the desired voltage state representing the data to be stored in a memory cell. A column decoder and sense amplifier are also connected to the bit line pair for reading data which has been stored in the memory cells. A bit line precharge circuit commonly accompanies the write driver circuit. The bit line precharge circuit operates to charge both lines of the bit line pair prior to a read or write operation.
The operation of the write driver and precharge circuit are crucial to the operation of the cache and thus the microprocessor. If the write driver does not work properly, wrong data or instructions will be stored or written into cache. The precharge circuit must also operate properly to ensure that the intended data is read during a read operation from cache. Without the proper precharge, an incorrect charge state may occur on the bit line pair during a read operation, resulting in incorrect data or instructions being read from memory.
Another problem arises during a read operation from the memory cells along the bit line pair. In a read operation, the logical high charge must be maintained on one of the bit lines of the pair. In the prior art, the charge is maintained only by a small transistor in the selected memory cell. However, the capacitance associated with the bit line and junction capacitance associated with the transfer gate device of the memory cells can cause the charge on the bit line to decay to an unacceptable level during a long read operation.